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Appendix C - EmWare System memory Map

Address RangeFunctionality
0000-BFFFUser RAM (FLEX applications run here)
C000-DFFFUser RAM (FLEX DOS runs here)
E000Exit key - write WINDOWS here in ASCII
E001Abort key - write ABORT here in ASCII
E002Flush key - write FLUSH here in ASCII
E003Case flip key - flips every time you write it
E004ACIA Control Register
E005ACIA Data Port
E006ACIA Control Register (Comm 1-4, if selected)
E007ACIA Data Port (Comm 1-4, if selected)
E008Mirror of E004 (ACIA Control Register)
E009Mirror of E005 (ACIA Data Port)
E00AUser r/w port 1; 1 bits = LED's red (both=yellow)
E00BUser r/w port 2; 1 bits = LED's green (both=yellow)
E00CRead-only emulator major ID (version)
E00DRead-only emulator minor ID (revision)
E00E-E00FReserved for future I/O, presently RAM
E010-E01FEmulator custom weirdness: Do Not Access!
E020RTC: Hundreds of years (IE 19 of 1997)
E021RTC: Tens & Ones of years (IE 97 of 1997)
E022RTC: Month (1=Jan)
E023RTC: Day of month (1-31)
E024RTC: Day of week (0-6, 0=Sunday)
E025RTC: Hour of day (1-24)
E026RTC: Minute of hour (0-59)
E027RTC: Seconds of Minute (0-59)
E028RTC: Strobe… takes snapshot of the time
E029Chunky code switch. R/W: 1=chunky 0=not.
E02A-E02FReserved for future I/O, presently RAM
E030VIA1 DATB Port B data register
E031VIA1 DATA Port A data register
E032VIA1 DDRB Port B data direction register
E033VIA1 DDRA Port A data direction register
E034VIA1 T1CL Timer 1 counter (low)
E035VIA1 T1CH Timer 1 counter (high)
E036VIA1 T1LL Timer 1 latch (low)
E037VIA1 T1LH Timer 1 latch (high)
E038VIA1 T2CL Timer 2 counter (low)
E039VIA1 T2CH Timer 2 counter (high)
E03AVIA1 SFTR Shift Register
E03BVIA1 ACRG Auxillary control register
E03CVIA1 PCRG Peripheral control register
E03DVIA1 IFRG interrupt flag register
E03EVIA1 IERG interupt enable register
E03FVIA1 DXTA port A data register (w/o handshake)
E040VIA2 DATB Port B data register
E041VIA2 DATA Port A data register
E042VIA2 DDRB Port B data direction register
E043VIA2 DDRA Port A data direction register
E044VIA2 T1CL Timer 1 counter (low)
E045VIA2 T1CH Timer 1 counter (high)
E046VIA2 T1LL Timer 1 latch (low)
E047VIA2 T1LH Timer 1 latch (high)
E048VIA2 T2CL Timer 2 counter (low)
E049VIA2 T2CH Timer 2 counter (high)
E04AVIA2 SFTR Shift Register
E04BVIA2 ACRG Auxillary control register
E04CVIA2 PCRG Peripheral control register
E04DVIA2 IFRG interrupt flag register
E04EVIA2 IERG interupt enable register
E04FVIA2 DXTA port A data register (w/o handshake)
E050VIA3 DATB Port B data register (Upper DIP Switch)
E051VIA3 DATA Port A data register (Lower DIP Switch)
E052VIA3 DDRB Port B data direction register
E053VIA3 DDRA Port A data direction register
E054VIA3 T1CL Timer 1 counter (low)
E055VIA3 T1CH Timer 1 counter (high)
E056VIA3 T1LL Timer 1 latch (low)
E057VIA3 T1LH Timer 1 latch (high)
E058VIA3 T2CL Timer 2 counter (low)
E059VIA3 T2CH Timer 2 counter (high)
E05AVIA3 SFTR Shift Register
E05BVIA3 ACRG Auxillary control register
E05CVIA3 PCRG Peripheral control register
E05DVIA3 IFRG interrupt flag register
E05EVIA3 IERG interupt enable register
E05FVIA3 DXTA port a data register (w/o handshake)
E060-E7FFReserved for future I/O, presently RAM
E800-F37FUser RAM (Unused by FLEX and Monitor)
F380-F7FFRAM (used by Psymon monitor… do not disturb)
F800-FFEFROM (Psymon) Monitor code; See PSYMON.TXT
FFF0-FFFFROM (Psymon) Interrupt & Reset vectors


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